Semiconductor memory devices, including but not limited to dynamic random access memories (DRAMs), static RAMs (SRAMs), and “pseudo” SRAMs (pSRAMS) typically include a number of memory cells that can be accessed in order to read data, write data, and/or refresh data. In such operations, a sense amplifier circuit can be utilized to sense the data value stored by an accessed memory cell.
While a semiconductor memory device may be designed to operate under some nominal set of conditions (e.g., temperature, power supply voltage), in actual applications such a device may have to operate under a wide range of conditions. At the extremes of such operating conditions, a semiconductor memory device may operate at unacceptably low speeds, or may operate erroneously.
One such adverse effect will now be described with reference to a conventional semiconductor memory device. Referring now to FIG. 8, a conventional memory device is shown in a schematic diagram and designated by the general reference character 800. A memory device 800 can include an array of memory cells 802, a sense amplifier circuit 804, and bit line (BL) multiplexer (MUX) circuits 806-0 and 806-1. In the particular example shown, an array of memory cells 802 can include DRAM memory cells, each of which includes a pass transistor and storage capacitor.
Selected of the memory cells of array 802 can be connected to a pair of bit lines 808-0 and 808-1. Bit line pair 808-0/1 can be connected to a sense amplifier circuit 804 by BL MUX circuit 806-0. FIG. 8 shows a shared sense amplifier arrangement, thus it is understood that BL MUX circuit 806-1 can connect a second bit line pair (not shown) to the same sense amplifier circuit 804.
Sense amplifier circuit 804 can include a pair of n-channel transistors N1/N2 and p-channel transistors P1/P2 arranged in a cross-coupled fashion between sense nodes 810-0 and 810-1. As is well understood, in a cross-coupled arrangement, a first transistor can have a gate coupled to the drain of a second transistor, and the second transistor can have a gate connected to the drain of the first transistor. N-channel sense transistors N1/N2 can be enabled (i.e., driven) by a signal “setn”. P-channel sense transistors P1/P2 can be enabled (i.e., driven) by a signal “setp”.
Sense amplifier circuit 804 can also include an equalization circuit formed by n-channel transistors N3/N4/N5. Equalization circuit N3/N4/N5 can be enabled by an equalization signal “bleql”. When activated, equalization circuit N3/N4/N5 can equalize sense amplifier nodes 810-0/1 to an equalization voltage “vbleq”.
FIG. 9 is a cross sectional representation of the circuit shown in FIG. 8. In the example shown, n-channel transistors (N1-N5) of the sense amplifier circuit 804, as well as the n-channel transistors of the BL MUXs (N6-N9) can be formed in a p-type substrate 902. P-channel transistors (P1-P2) of the sense amplifier circuit 804 can be formed in an n-type well 904 formed within p-type substrate 902. A p-type substrate 902 can be biased to a low power supply voltage VGND. An n-type well 904 can be biased to a high power supply voltage VCC.
FIG. 9 also illustrates how n-channel pass transistors within a memory cell array 802 can be formed in a p-type substrate 902. However, other arrangements are known, such as “triple well” arrangements in which a memory cells of array 802 can be formed a p-well formed within an n-well formed within a p-type substrate 902. In such arrangements, the p-well containing the memory cell can be “back” biased to a negative potential VBB.
While a conventional memory device like that illustrated in FIGS. 8 and 9 can operate adequately at nominal conditions, such a conventional arrangement can suffer from drawbacks at less than nominal conditions. One such drawback is illustrated in FIG. 10.
FIG. 10 is a timing diagram showing the response of the circuit shown in FIGS. 8 and 9 at an operating voltage and/or temperature lower than a nominal value. As shown by the figure, under such conditions, a bit line (in this case bit line BLC) may be driven to a sensed value at an undesirably slow rate. Said in another way, such a conventional sensing operation can “stall”.
The adverse effects of such operational conditions can be addressed in a number of conventional ways. In some cases, device operation is simply not ensured at lower temperatures and/or operating voltages. Such an approach undesirably limits the possible applications of the memory device.
In other conventional approaches, the transistors of a sense amplifier circuit can be fabricated to have lower threshold voltages than other transistors in the device. Such an approach adds complexity to the fabrication process, and may not always address a stall condition, particularly at substantially lower temperatures (e.g., less than 0° C.).
In light of the above, it would be desirable to arrive at some way of addressing sense amplifier response at lower temperatures and/or operating voltages that does not have the above drawbacks of conventional approaches.